This invention relates to a method of forming a metal fuse, and more particularly to a method of forming a metal fuse on or in a semiconductor device.
It is known to use fuses for circuit repair of semiconductor devices. For example, as the memory device or the device with an embedded memory, the defective memory cells can be replaced by blowing the related fuses with the redundancy row or column of the cells. So the yield of the memory devices can be improved. Also, logic devices can be repaired or reconfigured by blowing such fuses. For example, it is common to initially fabricate a generic logic chip having a large number of interconnected logic gates. Thereafter, in a final processing step, the chip is customized to perform the desired circuitry by blowing fuses.
Conventional metal fuses are formed on the penultimate, antepenultimate or deeper layer. The thickness of the oxide remaining over the fuse links is difficult to control using etching technology, particularly in processes wherein the devices are manufactured with thinner and thinner layers. The thick oxide remaining over the fuse causes at least two problems. The first problem is that a higher laser energy is needed to penetrate the remaining oxide in order to cut the fuse links. The higher laser energy may result in micro-cracking of the inter-metal dielectric layer, so that the reliability of the device is decreased. The second problem is that the remaining fuse link causes the failure of the laser repair when an insufficient amount of laser energy is utilized. Further, moisture and other contaminants can diffuse through the deep opening in such devices in the area where the fuse is located.
FIGS. 1A-B illustrate a prior art method of forming a conventional copper metal fuse and blowing the same. FIG. 1A is a cross sectional view of a conventional copper metal fuse semiconductor device. The copper metal fuse semiconductor device is provided by forming a conductive layer 22, such as a polysilicon layer, above the semiconductor substrate 10 and an isolation oxide layer 20. Then a first inter-level dielectric (ILD) layer 30 is formed and covers the entire substrate. Then an electrically conductive plug 32 is formed inside the first ILD layer 30. Thereafter, a copper metal conductive layer (first metallization layer) 34 is formed inside the first ILD layer 30 and makes electrical contact with the conductive plug 32.
Next, a first inter-metal dielectric (IMD) layer 40 is formed covering the first metallization layer 34 and the first ILD layer 30. Then a conductive plug 42 is formed inside the first IMD layer 40. Thereafter, a second metallization layer 44 is formed inside the first IMD layer 40 and makes electrical contact with the conductive plug 42.
Next, a second IMD layer 50 is formed covering the second metallization layer 44 and the first IMD layer 40. Then a conductive plug 52 is formed inside the second IMD layer 50. Thereafter, a third metallization layer 54 is formed inside the second IMD layer 50.
Next, a third IMD layer 60, conductive plug, 62 and fourth metallization layer 64 are made in a similar manner as described above. Likewise, a fourth IMD layer 70, conductive plug 72 and fifth metallization layer 76 are made in a similar manner as described above.
Next, a first passivation layer 92 such as silicon dioxide is formed over the fourth IMD layer 70 and fourth metallization layer 74. A second passivation layer 94, such as silicon nitride, may also be formed over the first passivation layer 92. Thereafter, conventional photolithography and etching techniques are used to pattern the passivation layers 92 and 94 and to open a fuse window 96. The IMD layer 60, typically silicon dioxide, is etched back over the fuse 56 to leave a dielectric layer 66 over the fuse 56 as shown in FIG. 1A.
Next the electrical probe test is performed to decide if the device cells or circuits need to be repaired. Thereafter, a laser beam 97 is emitted through the opening of the fuse window 96 and penetrates the remaining portion of the IMD layer (silicon dioxide) 66 to perform the laser repair. Thereafter, as shown in FIG. 1B, the fuse 56 is cut open by the laser beam. An opening 98 exposes the IMD layer 50 after the laser repair.
The fuse 56 is formed with the same mask as the conductive layer (third metallization layer) 54 so that thickness of the fuse 56 is the same as the conductive layer 54. A thinner fuse cannot be produced using this prior art method.
In the conventional method of fabricating such a fuse, as shown in the prior art FIGS. 1A-B, the fuse 56 is positioned deep below the surface of the device. Therefore, the laser energy must be substantially high to implement the laser repair. Still further, when the fuse 56 is positioned too deep in the structure, it is difficult for the laser beam to reach a focal point without part of the laser beam being dispersed. Hence, a substantial amount of the laser power is wasted. Typically, in response, a higher laser power is applied in an effort to provide a higher repair rate. However, turning up the laser power can easily damage part of the device area, for example by causing micro-cracking, and thus reduces the reliability of the process. Because of the very narrow window provided when the fuse is located in a position very deep within the device, it becomes difficult to vaporize the remaining oxide 66. When the thickness of the remaining oxide 66 is too thick, a greater amount of laser energy is required to blow the fuse and it is easy to cause the micro-cracking. However, if a lower laser energy is utilized to prevent micro-cracking, the fuse may not be sufficiently or completely cut. As a consequence, the laser energy window is very narrow in these prior art processes and devices. The present invention provides an improved method of forming a fuse on a semiconductor device, and in one embodiment forming a fuse on a semiconductor device produced using copper metallization techniques.
One embodiment of the invention includes a method of forming a metal fuse on the top metal conductive layer of a semiconductor device. Generally, the top metal conductive layer is thicker than the other metal conductive layers (metallization layers) in a semiconductor device. The present invention provides a method to reduce the thickness of the top metal fuse. In one embodiment, a specific additional mask is applied to form the metal fuse to reduce the thickness of the fuse. The method also includes forming a fuse window opening that is very shallow in the semiconductor device. The shallower opening allows for better control and removal of the remaining oxide left over the fuse during a fuse burning laser process. The thinner fuse and the thinner remaining oxide reduce the amount of laser energy required to vaporize the oxide and to cut the fuse. The location of the fuse also greatly enlarges the laser energy window that can be utilized to make laser repairs. The larger energy window results in a higher laser repair success ratio even if some deviation in the fabrication process occurs. Furthermore, device micro-cracking abnormality caused by using larger amounts of laser energy can be avoided. The prior art tendency to leave a metal fuse link as a result of using insufficient laser energy is also avoided.
Another embodiment of the invention includes a semiconductor device comprising:
a silicon based substrate, and a metallization layer overlying the silicon based substrate and a fuse portion, the metallization layer and the fuse portion being received in a dielectric layer, and the metallization layer having a thickness of at least 9000 angstroms, and the fuse portion having a thickness less than 4500 angstroms.
Another embodiment of the invention includes a method of making a semiconductor device having a thin fuse portion comprising: forming a first mask over a semiconductor device having a first metallization layer overlying a silicon based substrate and at least a first inter-metal dielectric layer overlying the first metallization layer, and wherein the first mask has an opening formed therein aligned with a portion of the first metallization layer;
etching through the first inter-metal dielectric layer down to the first metallization layer and removing the first mask to provide a first via through the first inter-metal dielectric layer down to the first metallization layer; forming a second mask over the semiconductor wafer and down into the first via formed through the first inter-metal dielectric layer, and etching a top portion of the second mask to leave a temporary plug in the first via in the first inter-metal dielectric layer; forming a third mask over the semiconductor wafer and into the via formed in the first inter-metal dielectric layer and on top of the temporary plug, and wherein the third mask has an opening therein spaced laterally a distance away from the temporary plug; etching a portion of the first inter-metal dielectric layer to form a shallow via therein to receive an electrically conductive material to form a fuse portion, and removing the third mask; forming a fourth mask over the semiconductor wafer and into the shallow via formed in the first inter-metal dielectric layer, and the fourth mask having an opening therein aligned with the temporary plug, etching a portion of the semiconductor wafer through the opening in the fourth mask to remove at least a portion of the first inter-metal dielectric layer and the temporary plug to provide a via down to the first metallization layer; forming an electrically conductive material over the semiconductor wafer and into the via down to the first metallization layer, and into the shallow via formed in the first inter-metal dielectric layer; removing a top portion of the electrically conductive material to form a second metallization layer and a plug extending down to the first metallization layer, and a fuse portion having a thickness less than the second metallization layer.
Another embodiment of the invention includes a method of making a semiconductor device having a thin fuse portion comprising: forming a first mask over a semiconductor device having a first metallization layer over a silicon based substrate and at least a first inter-metal dielectric layer overlying the first metallization layer and a second inter-metal dielectric layer overlying the first inter-metal dielectric layer, and wherein the first mask has an opening formed therein aligned with a portion of the first metallization layer; etching through the first and second inter-metal dielectric layers down to the first metallization layer and removing the first mask to provide a first via through the first inter-metal dielectric layer down to the first metallization layer; forming a second mask over the semiconductor wafer and down into the first via form through the first and second inter-metal dielectric layers, and etching a top portion of the second mask to leave a temporary plug in the first via in the first inter-metal dielectric layer; forming a third mask over the semiconductor wafer and into the first via formed in the first and second inter-metal dielectric layers and on top of the temporary plug, and wherein the third mask has an opening therein spaced laterally a distance away from the temporary plug; etching a portion of the second dielectric layer to form a shallow via therein to receive an electrically conductive material to form a fuse portion, and removing the third mask; forming a fourth mask over the semiconductor wafer and into the shallow via formed in the second inter-metal dielectric layer, and the fourth mask having an opening therein aligned with the temporary plug, and etching a portion of the semiconductor wafer through the opening in the fourth mask to remove at least a portion of the second inter-metal dielectric layer and the temporary plug to provide a via down to the first metallization layer; forming an electrically conductive material over the semiconductor wafer and into the via down to the first metallization layer and into the shallow via formed in the second inter-metal dielectric layer; removing a top portion of the electrically conductive material to form a second metallization layer and a plug extending down to the first metallization layer, and a fuse portion having a thickness less than the second metallization layer.
These and other embodiments of the present invention will become apparent from the following brief description of the drawings, detailed description of the preferred embodiments, and appended claims and drawings.